The following information was submitted:
Transactions: WSEAS TRANSACTIONS ON SYSTEMS
Transactions ID Number: 89-459
Full Name: Tripti Sharma
Position: Assistant Professor
Age: ON
Sex: Female
Address: FET-MITS, Lakshmangarh (Rajasthan)
Country: INDIA
Tel: +91-9413073681
Tel prefix:
Fax:
E-mail address: tripsha@gmail.com
Other E-mails: sharma.kg@gmail.com
Title of the Paper: A Novel CMOS 1-bit 8T Full Adder Cell
Authors as they appear in the Paper: tripti sharma, k.g.sharma, b.p.singh, neha arora
Email addresses of all the authors: tripsha@gmail.com, sharma.kg@gmail.com, bpsingh@ieee.org, neha.241986@gmail.com
Number of paper pages: 10
Abstract: The 1-bit full adder is a very important component in the design of application specific integrated circuits. Demands for the low power VLSI have been pushing the development of design methodologies aggressively to reduce the power consumption drastically. In most of the digital systems adder lies in the critical path that affects the overall speed of the system. So enhancing the performance of the 1-bit full adder cell is the main design aspect. The present study proposes a novel CMOS 1-bit full adder cell with least MOS transistor count that reduces the serious problem of threshold loss. It considerably increases the speed and also proves best for high frequency applications. Result shows 45% improvement in threshold loss problem and considerable reduction in power consumption over the other types of adders with comparable performance. The simulation has been carried out on Tanner EDA tool on BSIM3v3 90nm and 130nm technologies.
Keywords: Full adder, High speed,Low power, Power-delay product, XOR gate, VLSI
EXTENSION of the file: .pdf
Special (Invited) Session: High Speed, Low Power 8T Full Adder Cell with 45% Improvement in Threshold Loss Problem
Organizer of the Session: 643-411
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