The following information was submitted:
Transactions: INTERNATIONAL JOURNAL of CIRCUITS, SYSTEMS and SIGNAL PROCESSING
Transactions ID Number: 19-102
Full Name: Ahmed Saeed
Position: Assistant
Age: ON
Sex: Male
Address: 15th May city, Group 32 Block 16-B
Country: EGYPT
Tel: 0020102052382
Tel prefix:
Fax:
E-mail address: saeeed3@yahoo.com
Other E-mails: asaeed@fue.edu.eg
Title of the Paper: Efficient FPGA implementation of FFT/IFFT Processor
Authors as they appear in the Paper: Ahmed Saeed, M. Elbably, G. Abdelfadeel, and M. I. Eladawy
Email addresses of all the authors: saeeed3@yahoo.com, elbably_55@yahoo.com, gam_hel@yahoo.com, mohamed@eladawy.com
Number of paper pages: 8
Abstract: The Fast Fourier Transform (FFT) and its inverse (IFFT) are very important algorithms in signal processing, software-defined radio, and the most promising modulation technique; Orthogonal Frequency Division Multiplexing (OFDM). This paper explains the implementation of radix-22 single-path delay feedback pipelined FFT/IFFT processor. This attractive architecture has the same multiplicative complexity as radix-4 algorithm, but retains the simple butterfly structure of radix-2 algorithm. The implementation was made on a Field Programmable Gate Array (FPGA) because it can achieve higher computing speed than digital signal processors, and also can achieve cost effectively ASIC-like performance with lower development time, and risks. The processor has been developed using hardware description language VHDL on an Xilinx xc5vsx35t and simulated up to 465MHz and exhibited execution time of 0.135μS for transformation length 256-point. This results show that the process!
or achieves higher throughput and lower area and latency.
Keywords: FFT, FPGAs, Radix-22 single-path delay feedback (R22SDF), Pipelining, VHDL.
EXTENSION of the file: .pdf
Special (Invited) Session: FPGA implementation of Radix-22 Pipelined FFT Processor
Organizer of the Session: 614-429
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