The following information was submitted:
Transactions: WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS
Transactions ID Number: 53-689
Full Name: Krishnasamy natarajan Vijeyakumar
Position: Assistant Professor
Age: ON
Sex: Male
Address: Department of Electronics and Communication Engineering, Anna University of Technology, Coimbatore
Country: INDIA
Tel: +919942377050
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E-mail address: vijey.tn@gmail.com
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Title of the Paper: Design of Low Power Full Adder Using Active Level Driving Circuit
Authors as they appear in the Paper: Krishnasamy natarajan Vijeyakumar, Vembu Sumathy, Mahendran Nithya, Chinnaraj Venkatnarayanan and Velusamy Thiruchitrabala
Email addresses of all the authors: vijey.tn@gmail.com, sumi2001_gct@yahoo.co.in, nitmahendran@yahoo.co.in, vimhalc@gmail.com and thiruchitrabala@gmail.com
Number of paper pages: 10
Abstract: CMOS technology is approaching the nano-electronics range nowadays, but experiences some practical limits. High dynamic power dissipation and leakage current in deep submicron technologies contribute a major proportion of total power dissipation in CMOS circuits designed for portable applications. Consequently, identification and modeling of different components is very important for estimation and reduction of power dissipation in scaled CMOS circuits, especially for low power applications. As full adder (FA) forms one of the important unit of digital signal processing architecture , its design implementation is considered. The logic styles used in the design of CMOS full adder circuit have many limitations in terms of power and number of transistors. Pseudo NMOS-PT adder is designed with carry block in Pseudo NMOS logic for reducing dynamic power dissipation and sum block in pass transistor logic for reducing gate count. An Active Level Driving Circuit(ALDC) !
is proposed for driving the level restoring weak PMOS pull-up transistor. ALDC charges the gate of pull up PMOS transistor to Vdd for active low outputs, turning it to OFF . This reduces the leakage power dissipation thereby decreasing the total power dissipation. The proposed adder is designed using Tanner 7.0 and simulated using TSPICE. Fabrication technology used is 180nm. Performance analysis reveals that the proposed adder design fairs better than conventional static CMOS, CPL, CMOS-BBL and BBL-PT adders in terms of power, delay and power delay product (PDP). Design implementation with Carry Select Adder (CSLA) is considered to measure driving capability.
Keywords: CPL, TGA, hybrid adder, BBL-PT, Pseudo NMOS, Portable application.
EXTENSION of the file: .pdf
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