The following information was submitted:
Transactions: WSEAS TRANSACTIONS ON ELECTRONICS
Transactions ID Number: 29-279
Full Name: Yandra Rajasree
Position: Professor
Age: ON
Sex: Female
Address: HIG 315,Phase 1, BHEL Toenship, R.C.Puram,Hyderabad
Country: INDIA
Tel: 040 23027813
Tel prefix: 91
Fax: 91 040 23027813
E-mail address: rajasreey@yahoo.com
Other E-mails: ynmtitanium@yahoo.com
Title of the Paper: Methodical self checking and test infrastructure design for fault tolerance in digital circuits
Authors as they appear in the Paper: Rajasree Yandra , Y.Vishnu Priya , N.R.Alamelu
Email addresses of all the authors: rajasreey@yahoo.com, yandra_priya@gmail.com,nra@vinayakamissions.com
Number of paper pages: 10
Abstract: During the process of development of any system, system reliability is of utmost importance .Specially when designing a processor, it is desired that a processor function correctly even in the presence of faults .This concept is commonly referred to as fault tolerance. The fault tolerant microprocessor systems used in safety critical applications need to be thoroughly validated during the design stages. As feature size reduces in future, there is an increased probability of transient and intermittent faults. Transient faults can only detected by online detection or concurrent checking and not by testing . Because of continuously shrinking dimensions and voltage levels in near future transient faults will be a major source of errors. Therefore concurrent checking is becoming all the more important and necessary. Now these systems on chip integrated circuits contain both digital and analog cores. Test cost for such mixed signal SOC is much higher than the digital SO!
C that allows the analog and digital cores to be tested. The analog cores are wrapped such that the test can performed using a digital test access mechanism .In our method , an analog test infrastructure is used which consists of test wrappers and test access mechanism. Test wrappers isolate various modules from their surrounding circuitry during test .So the focus is on optimisation of a unified test access architecture that is used for digital and analogue cores. We wrap each analog core by a pair of digital to analog converter and analog to digital converter .They convert analog core to virtual digital core which allow the use of digital testers to test the analog cores. This reduces the need for expensive mixed signal tester so that there is a reduction in the overall cost. The work demonstrates an implementation of a design methodology for embedding fault tolerant capabilities into high level digital system design.
Keywords: Fault, multiplier, adder, wrapper, carry, ADC, synthesis, sampling
EXTENSION of the file: .doc
Special (Invited) Session: Self checking and fault tolerant digital design
Organizer of the Session: 612-197R
How Did you learn about congress: Dr.S.K.Srivatsa sksrivatsa@yahoo.com
IP ADDRESS: 115.241.48.209
