The following information was submitted:
Transactions: WSEAS TRANSACTIONS ON COMPUTERS
Transactions ID Number: 29-277
Full Name: Kapil Gwalani
Position: Student
Age: ON
Sex: Male
Address: 915, Laurel Avenue, Apt. W3E, Cookeville, TN.
Country: UNITED STATES
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E-mail address: kagwalani21@tntech.edu
Other E-mails: OElkeelany@tntech.edu
Title of the Paper: Design and Evaluation of FPGA Based Hardware Accelerator for Elliptic Curve Cryptography Scalar Multiplication
Authors as they appear in the Paper: Kapil A. Gwalani, Omar Elkeelany
Email addresses of all the authors: Kagwalani21@tntech.edu , OElkeelany@tntech.edu
Number of paper pages: 10
Abstract: Abstract: Embedded systems find applications in fields such as defense, communications, industrial automation and many more. For majority of these applications, security is a vital issue. Over the last decade, security has become the primary concern when discussing e-commerce. The rapid development in the field of information technology has led to the increase in need of techniques capable of providing security. Cryptography plays an important role in providing data security. Until recently, symmetric key encryption schemes were used for a majority of these applications. Now however, asymmetric key encryption schemes such as Elliptic curve cryptography are gaining popularity as they require less computational power and memory and are still capable of providing equivalent security when compared to their counterparts. Elliptic curve cryptography was first introduced in 1985 and has always been around since. Scalar or point multiplication in elliptic curve cryptograph!
y has been a topic of research interest. Improving the performance of scalar multiplication can improve the overall performance of elliptic curve cryptography. One popular method to improve scalar multiplication is by means of hardware accelerators. The authors of this paper have implemented scalar multiplication, the most time consuming operation in elliptic curve cryptography using binary non-adjacent form algorithm. The results of the software implementation have been presented in section- 4. Methodology to improve the performance of the scalar multiplication by use of hardware accelerators has also been presented in this paper.
Keywords: Binary Non Adjacent Form, ECC, Prime Field, System on Progrmmable Chip
EXTENSION of the file: .pdf
Special (Invited) Session: Design and Evaluation of Hardware Accelerator for Elliptic Curve Cryptography Point Multiplication
Organizer of the Session: 612-411
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