The following information was submitted:
Transactions: WSEAS TRANSACTIONS ON COMPUTERS
Transactions ID Number: 53-500
Full Name: Dhulipala Krishnaveni
Position: Assistant Professor
Age: ON
Sex: Female
Address: Jakkasandra Post, Ramanagara Taluk, Kanakapura, Bangalore,Karnataka
Country: INDIA
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E-mail address: mailkveni@gmail.com
Other E-mails: pidaparthi@hotmail.com
Title of the Paper: A Novel Design of Reversible Universal Shift Register with Reduced Delay and Quantum Cost
Authors as they appear in the Paper: D.Krishnaveni, M.Geetha Priya
Email addresses of all the authors: mailkveni@gmail.com,geetha.sri82@gmail.com
Number of paper pages: 11
Abstract: Reversible logic gates provide power optimization which can be used in low power CMOS design, optical computing, quantum computing and nanotechnology. This paper proposes a new 3 * 3 reversible SRK gate that works as a reversible 2:1 Multiplexer and has a reduced quantum cost. A novel design of Reversible Universal Shift Register using SRK gates with reduced delay and quantum cost is proposed. Reduction of delay, which is a major factor contributing to the improvement of efficiency of the circuit is adequately taken care in all the components of the proposed design. Thus, this paper provides a threshold to build more complex sequential systems using reversible logic.
Keywords: Low power CMOS; quantum computing; Reversible logic gates; Universal Shift Register; quantum cost, Sequential circuits
EXTENSION of the file: .doc
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How Did you learn about congress: Reversible logic gates, reversible universal shift register, quantum cost, sequential circuits, D Flip flops, master slave D Flip flops
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