The following information was submitted:
Transactions: WSEAS TRANSACTIONS ON COMMUNICATIONS
Transactions ID Number: 29-589
Full Name: Tsai-Sheng Kao
Position: Assistant Professor
Age: ON
Sex: Male
Address: No. 111 Gong Jhuan Road, Chung Ho, Taipei County 23568, Taiwan, R.O.C. (Department of Electronic Engineering, Hwa-Hsia Institute of Technology)
Country: TAIWAN
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E-mail address: tsaishengkao@gmail.com
Other E-mails: tskao@cc.hwh.edu.tw
Title of the Paper: Extended Kalman Filtering and Phase Detector Modeling for a Digital Phase-Locked Loop
Authors as they appear in the Paper: Tsai-Sheng Kao, Sheng-Chih Chen, Yuan-Chang Chang, Sheng-Yun Hou, and Chang-Jung Juan
Email addresses of all the authors: tsaishengkao@gmail.com, tskao@cc.hwh.edu.tw
Number of paper pages: 10
Abstract: The realization of a digital phase-locked loop (DPLL) quires to choose a suitable phase detector and to design an appropriate loop filter; these tasks are commonly nontrivial in most applications. In this paper, the phase detector is examined, and a simple model is given to describe the characteristics of the timing function. The DPLL system is then formulated as a state estimation problem; then an extended Kalman filter (EKF) is applied to realize this DPLL for estimating the sampling phase. Therefore, the phase detector and loop filter are simply realized by the EKF. The proposed DPLL has a simple structure and low realization complexity. Computer simulations for a conventional DPLL system are given to compare with those for the proposed timing recovery system. Simulation results indicate that the proposed realization can estimate the input phase rapidly without causing a large jittering.
Keywords: Digital phase-locked loop (DPLL), phase detector, state estimation, extended Kalman filter (EKF)
EXTENSION of the file: .pdf
Special (Invited) Session: Digital Phase-Locked Loop and its Realization
Organizer of the Session: 618-471
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