The following information was submitted:
Transactions: INTERNATIONAL JOURNAL of CIRCUITS, SYSTEMS and SIGNAL PROCESSING
Transactions ID Number: 17-270
Full Name: Tsai-Ming Hsieh
Position: Professor
Age: ON
Sex: Male
Address: 200, Chung Pei Road, Chung-Li, 32023, Taiwan
Country: TAIWAN
Tel: +886-3-2654708
Tel prefix:
Fax: +886-3-2654799
E-mail address: hsieh@cycu.edu.tw
Other E-mails: pp022@mail.lhu.edu.tw
Title of the Paper: 3D Partitioning for Interference and Area Minimization
Authors as they appear in the Paper: Hsin-Hsiung Huang and Tsai-Ming Hsieh
Email addresses of all the authors: hsieh@cycu.edu.tw,pp022@mail.lhu.edu.tw
Number of paper pages: 8
Abstract: This work defines a novel problem in which a set of modules is assigned to a set of silicon layers in order to minimize the total chip area while satisfying the characteristic constraints. An integer linear programming (ILP)-based partitioning approach is also developed to assign a set of modules to the layers of a three-dimensional architecture during a floor-planning phase. The proposed approach attempts to minimize the chip area, which is the maximum silicon layer area among the set of layers in a three-dimensional system-in-package (SIP) architecture. Moreover, the circuit properties in which the digital and analog modules not to assign to the same layer are incorporated to increase signal integrity during the partitioning stage. The optimal module assignment for the three-dimensional SIP architecture could be obtained because all the constraints in this work are linear functions. Experimental results indicate that the proposed ILP-based method can minimize the!
chip area while meeting the SIP constraints of circuit properties to reduce the potential interference of the wires in the digital and analog modules. The chip area is larger than that of the method that does not consider interference properties of modules. Importantly, the proposed ILP-based approach significantly reduces the number of the potential interference to be zero by assigning analog and digital modules to the different layers of the SIP architecture.
Keywords: Interference, SIP-ware partitioning, integer linear programming, area minimization.
EXTENSION of the file: .pdf
Special (Invited) Session: 3D Area-Aware Partitioning for Floorplanner
Organizer of the Session: 303-165
How Did you learn about congress:
IP ADDRESS: 140.131.13.81
