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Transactions: WSEAS TRANSACTIONS ON SIGNAL PROCESSING
Transactions ID Number: 31-765
Full Name: Yuan-ping Li
Position: Ph.D. Candidate
Age: ON
Sex: Male
Address: 135, Yuan-Tung Rd., Chungli City 32026, Taiwan
Country: TAIWAN
Tel: +886-3-4638800 Ext. 7011/833
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E-mail address: s909107@mail.yzu.edu.tw
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Title of the Paper: modular design and implementation of fpga-based tap-selective maximum-likelihood channel estimator
Authors as they appear in the Paper: Jeng-kuang Hwang,Yuan-ping Li
Email addresses of all the authors: eejhwang@saturn.yzu.edu.tw,s909107@mail.yzu.edu.tw
Number of paper pages: 10
Abstract: The modular design of the optimal tap-selective maximum-likelihood (TSML) channel estimator based on field-programmable gate array (FPGA) technology is studied. A novel range reduction algorithm is included in the natural logarithmic function (NLF) emulator based on the coordinate rotation digital computer (CORDIC) methodology and is integrated into the TSML channel estimator system. The low-complexity TSML algorithm, which is employed for sparse multipath channel estimation, is proposed for long-range broadband block transmission systems. Furthermore, the proposed range reduction algorithm aims to solve the limited interval problem in the CORDIC algorithm base on Xilinx¡¦s SG platforms. The modular approach facilitates the reuse of modules.
Keywords: Coordinate rotation digital computer (Cordic), Fpga design, Maximum-likelihood channel estimation, Range reduction, Logarithm function, Parallel sorting
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