The following information was submitted:
Transactions: WSEAS TRANSACTIONS ON SIGNAL PROCESSING
Transactions ID Number: 53-489
Full Name: Tze-Yun Sung
Position: Professor
Age: ON
Sex: Male
Address: 707, Sec. 2, Wufu Road, Hsinchu City 300-12
Country: TAIWAN
Tel: 886-3-518-6387
Tel prefix: 886-3-518-6890
Fax: 886-3-518-6891
E-mail address: bobsung@chu.edu.tw
Other E-mails: bobsung@ms41.hinet.net
Title of the Paper: VLSI Implementation of 3-D CORDIC-Based Vector Interpolator in Power-Aware Graphic System
Authors as they appear in the Paper: Tze-Yun Sung, Yaw-Shieh Shieh, Hsi-Chin Hsin
Email addresses of all the authors: bobsung@chu.edu.tw,ysdaniel@chu.edu.tw,hsin@nuu.edu.tw
Number of paper pages: 10
Abstract: High performance architectures for the data intensive and latency restrained applications can be achieved by maximizing both parallelism and pipelining. In this paper, the COordinate Rotation DIgital Computer (CORDIC) based hardware primitives of 3-D rotation with high throughput 3-D CORDIC-based vector interpolation are presented. The proposed architecture for 3-D CORDIC-based vector interpolator, which is based on the CORDIC redundant arithmetic, has been implemented by VLSI and achieve up to energy saving without image quality degradation. The graphic system is power-aware.
Keywords: Redundant arithmetic, CORDIC, 3-D vector interpolation, Rendering, VLSI, Power-aware.
EXTENSION of the file: .pdf
Special (Invited) Session: Image Processing and 2-D / 3-D Systems
Organizer of the Session: Richard Choras,Nikos E. Mastorakis,Valeri Mladenov
How Did you learn about congress: Architectures and VLSI hardware,Image Processing
IP ADDRESS: 140.126.127.50
