The following information was submitted:
Transactions: WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS
Transactions ID Number: 29-324
Full Name: Tze-Yun Sung
Position: Professor
Age: ON
Sex: Male
Address: 707, Sec. 2, wufu Road, Hsinchu City 300-12
Country: TAIWAN
Tel: +886-3-518-6387
Tel prefix:
Fax: +886-3-518-6891
E-mail address: bobsung@chu.edu.tw
Other E-mails: bobsung@ms41.hinet.net
Title of the Paper: Reconfigurable VLSI Architecture for FFT Processor
Authors as they appear in the Paper: Tze-Yun Sung, Hsi-Chin Hsin, Lu-Ting Ko
Email addresses of all the authors: bobsung@chu.edu.tw, hsin@nuu.edu.tw, m09601049@chu.edu.tw
Number of paper pages: 10
Abstract: This paper presents a reusable intellectual property (IP) Coordinate Rotation Digital Computer (CORDIC)-based split-radix fast Fourier transform (FFT) core for orthogonal frequency division multiplexer (OFDM) systems, for example, Ultra Wide Band (UWB), Asymmetric Digital Subscriber Line (ADSL), Digital Audio Broadcasting (DAB), Digital Video Broadcasting ¡V Terrestrial (DVB-T), Very High Bitrate DSL (VHDSL), and Worldwide Interoperability for Microwave Access (WiMAX). The high-speed 128/256/512/1024/2048/4096/8192-point FFT processors and programmable FFT processor have been implemented by 0.18 (1p6m) at 1.8V, in which all the control signals are generated internally. These FFT processors outperform the conventional ones in terms of both power consumption and core area.
Keywords: IP, FFT, CORDIC, split-radix, OFDM systems
EXTENSION of the file: .pdf
Special (Invited) Session: Reconfigurable VLSI Architecture for FFT Processor
Organizer of the Session: 613-231
How Did you learn about congress: kuo-Jen Lin(kuojenlin@chu.edu.tw), Shen-Fu Hsiao [sfhsiao@cse.nsysu.edu.tw]
IP ADDRESS: 114.45.96.198
