The following information was submitted:
Transactions: WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS
Transactions ID Number: 89-660
Full Name: James Parkerson
Position: Associate Professor
Age: ON
Sex: Male
Address: 1 University of Arkansas, JBHT 520, Fayetteville, AR 72701
Country: UNITED STATES
Tel: 1-479-575-6039
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E-mail address: jparkers@uark.edu
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Title of the Paper: Adder Designs using Reversible Logic Gates
Authors as they appear in the Paper: p. k. lala, j. p. parkerson, p. chakraborty
Email addresses of all the authors: plala@tamut.edu, jparkers@uark.edu, pchakrab@uark.edu
Number of paper pages: 10
Abstract: A new reversible logic gate was proposed in Ref. [1]. This gate can be used to implement any classical Boolean logic function. This paper shows the application of the reversible gate in implementing ripple carry, carry skip and carry look-ahead adders. These adders are more efficient than adders implemented using Fredkin Gates
Keywords: reversible logic, Fredkin gate, garbage output, adder design
EXTENSION of the file: .doc
Special (Invited) Session: On Adder Design using a Reversible Logic Gate
Organizer of the Session: 640-796
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