The following information was submitted:
Transactions: WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS
Transactions ID Number: 89-658
Full Name: Tze-Yun Sung
Position: Professor
Age: ON
Sex: Male
Address: 707, Sec. 2, Wufu Road, Hsinchu City 300-12
Country: TAIWAN
Tel: +886-3-518-6387
Tel prefix:
Fax: +886-3-518-6891
E-mail address: bobsung@chu.edu.tw
Other E-mails: bobsung@ms41.hinet.net
Title of the Paper: Multiplierless, Reconfigurable Folded Architecture for VLSI Wavelet Filter
Authors as they appear in the Paper: Tze-Yun Sung, Hsi-Chin Hsin, Sheng-Dong Chang
Email addresses of all the authors: bobsung@chu.edu.tw, hsin@nuu.edu.tw, 985401004@cc.ncu.edu.tw
Number of paper pages: 11
Abstract: In this paper, the high-efficient and reconfigurable architectures for the 9/7-5/3 discrete wavelet transform (DWT) based on convolution scheme are proposed. The proposed parallel and pipelined architectures consist of a high-pass filter (HF) and a low-pass filter (LF). The critical paths of the proposed architectures are reduced. Filter coefficients of the biorthogonal 9/7-5/3 wavelet low-pass filter are quantized before implementation in the high-speed computation hardware. In the proposed architectures, all multiplications are performed using less shifts and additions. The proposed reconfigurable architecture is 100% hardware utilization and ultra low-power. The proposed reconfigurable architectures have regular structure, simple control flow, high throughput and high scalability. Thus, they are very suitable for new-generation image compression systems, such as JPEG-2000.
Keywords: Folded reconfigurable architecture, 9/7-5/3 discrete wavelet transform (DWT), high-pass filter (HF), low-pass filter (LF), convolution scheme.
EXTENSION of the file: .pdf
Special (Invited) Session: Folded Reconfigurable Architecture for VLSI Wavelet Filte
Organizer of the Session: 637-134
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