The following information was submitted:
Transactions: WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS
Transactions ID Number: 42-385
Full Name: Changhong Yu
Position: Doctor (Researcher)
Age: ON
Sex: Male
Address: Department of Information & Electronic Engineering Zhejiang Gongshang University
Country: CHINA
Tel: +8613858033500
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Fax:
E-mail address: hangzhouyu@gmail.com
Other E-mails: yuch_2007@163.com,chentianding@163.com
Title of the Paper: Fault Tolerance Design by Accurate SER Estimation for Nano-Scale Circuits
Authors as they appear in the Paper: Changhong Yu, Tianding Chen
Email addresses of all the authors: hangzhouyu@gmail.com,chentianding@163.com
Number of paper pages: 10
Abstract: As the transistor sizes continue to shrink, quantum effects will significantly affect the circuit behavior. The inherent unreliability of nano-electronics will have significantly impact on the way of circuits design, so defects and faults of nano-scale circuit technologies have to be taken into account early in the design of digital systems. Fault-tolerant architectures may become a necessity to ensure that the underlying circuit could function properly. In CAD software, a same logic can be made out with different circuits but different design methodology can reach different soft error tolerance ability, so we must find a way to estimate the error rate of the circuit efficiently to make the design more fault tolerant. In this paper, a new way to fault tolerance design in nano-scale circuit by accurate soft error rate (SER) estimation is proposed. Transform matrix is used for SER computation and a design criteria is then proposed. Simulation results show that the p!
roposed transform matrix model is effective for nano-scale circuits and the criteria delivered is suitable CAD tools development in nano-system design.
Keywords: Nano-system, SER estimation, Transform matrix, Matrix analysis, Condition number, Fault tolerance design
EXTENSION of the file: .doc
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