The following information was submitted:
Transactions: WSEAS TRANSACTIONS ON SIGNAL PROCESSING
Transactions ID Number: 53-709
Full Name: Krishnasamy natarajan Vijeyakumar
Position: Ph.D. Candidate
Age: ON
Sex: Male
Address: Department of ECE,Anna University of Technology,Coimbatore
Country: INDIA
Tel: +919942377050
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E-mail address: vijey.tn@gmail.com
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Title of the Paper: Design of Low- Power Low-area Error Tolerant Shift and Add Multiplier
Authors as they appear in the Paper: Krishnasamynatarajan Vijeyakumar,Vembu Sumathy, Sriram Komanduri, Christopher Chrisjin gnana suji
Email addresses of all the authors: vijey.tn@gmail.com,sumi2001_gct@yahoo.co.in,komanduri.sriram@gmail.com,chrisjin_suji@yahoo.co.in
Number of paper pages: 10
Abstract: In this paper, a low power multiplier architecture for high speed arithmetic is proposed. The modifications to conventional shift and add multiplier includes the introduction of modified error tolerant technique for addition, and enabling of adder cell by current multiplication bit of the multiplier constant. The proposed architecture enables the removal of input multiplexer, switching OFF of adder cells and bypassing adder for zero bit values of the multiplier constant. The architecture makes use of down counter for tracking shift of partial products and multiplier bits. Simulation results of the proposed design in 8 X 8 multiplier architecture shows that power consumption is reduced by 23.8% and area by 35.6% compared to the conventional shift-and add multiplier. The proposed architecture can be used for portable image processing applications where minimum percentage of error is tolerable.
Keywords: High speed arithmetic, Error tolerant technique, Down counter, Partial Product (PP), Digital signal processing, Image processing.
EXTENSION of the file: .doc
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How Did you learn about congress: Digital signal processing, VLSI signal processing, Low power VLSI design.
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