The following information was submitted:
Transactions: WSEAS TRANSACTIONS ON ELECTRONICS
Transactions ID Number: 32-345
Full Name: Syed Saud Naqvi
Position: Lecturer
Age: ON
Sex: Male
Address: Park Road chak Shahzad Campus CIIT Islamabad Pakistan
Country: PAKISTAN
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Tel prefix:
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E-mail address: saudnaqvi82@hotmail.com
Other E-mails: saud_naqvi@comsats.edu.pk
Title of the Paper: Application Specific Scalable Architectures for Advanced Encryption Standard (AES) Algorithm
Authors as they appear in the Paper: S.s.Naqvi, S.r.Naqvi, S.a Khan, S.a. Malik
Email addresses of all the authors: saud_naqvi@comsats.edu.pk, rameeznaqvi83@hotmail.com, shahidk@comsats.edu.pk, smalik@comsats.edu.pk
Number of paper pages: 10
Abstract: The work presented proposes two diverse FPGA based architectures with high-speed and low area constraints for suitable implementation of Advanced Encryption Standard (AES). The main focus of this paper is to compare different design architectures existing in literature with the proposed ones, based on application specific constraints. The high speed design presented here proposes a good engineering solution to high speed applications where area constraint can not be totally neglected. The high speed design manages to achieve a reasonable 6 Gbps throughput despite of the fact that it only covers mere 5800 slices in area .Low area architecture achieves a decent throughput of 1.98 Mbps with low slices count of 297. Some common applications of high speed design include broadband switches and firewall, whereas the low area design mainly focuses on compact applications like PDAs and cell phone in which area and power constraints are critical. Both the designs are impleme!
nted and tested using a Xilinx Spartan-III (XC3S2000) target device.
Keywords: Advanced encryption standard (AES), Subpipelined, High speed, Low area, Unrolled architecture, Cryptography, Throughput, FPGA, and Data encryption standard (DES).
EXTENSION of the file: .doc
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