The following information was submitted:
Transactions: WSEAS TRANSACTIONS ON COMPUTERS
Transactions ID Number: 29-805
Full Name: Ion Bucur
Position: Associate Professor
Age: ON
Sex: Male
Address: Str. Pastorului nr.1, Bl. 3, Sc. B, Ap. 60, 020348, Bucharest
Country: ROMANIA
Tel: 726 325 795
Tel prefix: +40
Fax:
E-mail address: ion.bucur@cs.pub.ro
Other E-mails: ion.bebe.bucur@gmail.com
Title of the Paper: Power-Aware, Depth-Optimum and Area Minimization Mapping of K-LUT Based FPGA Circuits
Authors as they appear in the Paper: Ion Bucur, Nicolae Cupcea, Adrian Surpateanu, Costin Stefanescu, Florin Radulescu
Email addresses of all the authors: ion.bucur@cs.pub.ro, nicolae.cupcea@cs.pub.ro, adrian.surpateanu@cs.pub.ro, costin.stefanescu@cs.pub.ro, florin.radulescu@cs.pub.ro
Number of paper pages: 13
Abstract: This paper introduces an efficient application intended for mapping under complex criteria applied to K-LUT based FPGA implemented circuits. This application is based on an algorithm that was developed taking into consideration a significant design factor - power consumption. Power consumption is considered in addition to other design factors that are traditionally used. To increase performance, it was used a flexible mapping tool based on exhaustive generation of all K-bounded sub-circuits rooted in each node of the circuit. Achieved information about logic dissipated power was obtained using an efficient dedicated simulator. In addition to lower power consumption, we devised several effective mapping techniques designed for reducing area and optimum depth.
Keywords: Power-aware, Optimal area, K-LUT based FPGA, Logic activity simulator, Functional power
EXTENSION of the file: .pdf
Special (Invited) Session: Heuristic Performance Optimal and Power Conscious for K-LUT Based FPGA Technology Mapping
Organizer of the Session: 625-164
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