The following information was submitted:
Transactions: INTERNATIONAL JOURNAL of CIRCUITS, SYSTEMS and SIGNAL PROCESSING
Transactions ID Number: 20-450
Full Name: Victor Jimenez-Fernandez
Position: Doctor (Researcher)
Age: ON
Sex: Male
Address: Circuito Gonzalo Aguirre Beltran S/N, zona universitaria
Country: MEXICO
Tel: 228 8421746
Tel prefix: (52)
Fax: (52)228 8421746
E-mail address: vicjimenez@uv.mx
Other E-mails: vjimenez@inaoep.mx
Title of the Paper: digital circuit architecture for a median filter of grayscale images based on sorting network
Authors as they appear in the Paper: Victor Jimenez-Fernandez, Denisse Martinez-Navarrete, Carlos Ventura-Arizmendi, Zulma Hernandez-Paxtian, Joel Ramirez-Rodriguez
Email addresses of all the authors: vicjimenez@uv.mx,same_98@hotmail.com,cventura7@hotmail.com,zpaxtian@hotmail.com,joel290390@hotmail.com
Number of paper pages: 8
Abstract: In this paper a digital circuit architecture dedicated to median filtering of grayscale images is presented. The architecture emerges from a sorting network based median algorithm which effectiveness is verified by Matlab programming and its hardware implementation tested on a Spartan-3E FPGA device. The median pixel computation is approached by a sorting network scheme which is constituted by seven three-data comparator modules and hierarchically composed by twenty one switch/compare circuits. The successful operation of the three-data comparator module is demonstrated by transistor level SPICE simulations using 0.5um CMOS technology.
Keywords: Digital architecture, Grayscale image, Median filter, Sorting network, Transistor level
EXTENSION of the file: .pdf
Special (Invited) Session: digital architecture for a median filter of image based on sorting network
Organizer of the Session: 649-228
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