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Transactions: WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS
Transactions ID Number: 53-197
Full Name: Padmanabhan Balasubramanian
Position: Doctor (Researcher)
Age: ON
Sex: Male
Address: School of Computer Science, The University of Manchester, Manchester M13 9PL
Country: UNITED KINGDOM
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E-mail address: padmanab@cs.man.ac.uk
Other E-mails: spbalan04@gmail.com
Title of the Paper: A Robust Asynchronous Early Output Full Adder
Authors as they appear in the Paper: Padmanabhan Balasubramanian
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Number of paper pages: 10
Abstract: A robust asynchronous full adder design corresponding to early output logic, synthesized using the elements of a standard cell library is presented in this paper. As the name suggests, the adder ensures gate orphan freedom and neatly fits into the self-timed system architecture. In comparison with many of the indicating full adder designs, which can be embedded in the self-timed system, it is found that the proposed full adder enables reduction in latency by 20.7%, occupies lesser area by 15.4% and features minimized average power dissipation by 8.6% against the best design metrics of its counterparts. These design estimates correspond to simulation results of the 32-bit carry-ripple adder circuit; derived by targeting a high-speed 130nm bulk CMOS process technology. Also, the proposed full adder facilitates a faster reset and the return-to-zero for the fundamental carry-propagate topology is achieved with only two full adder delays.
Keywords: Full adder, Asynchronous design, Early propagation, Indication, Standard cells, CMOS process
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