The following information was submitted:
Transactions: WSEAS TRANSACTIONS ON COMPUTERS
Transactions ID Number: 32-781
Full Name: Jestin Rajamony
Position: Senior Lecturer
Age: ON
Sex: Male
Address: CSI Institute of Technology, Grace Garden, Thovalai,
Country: INDIA
Tel: 04652-263176, 09486550074
Tel prefix:
Fax:
E-mail address: jestin_br@yahoo.com
Other E-mails: jestin_br123@rediffmail.com, jestinbr@gmail.com
Title of the Paper: Section Code Task Model For Heterogeneous Processor In Real Time System
Authors as they appear in the Paper: Jestin Rajamony , K.Ramar, K.P.Ajitha Gladis
Email addresses of all the authors: jestin_br@yahoomail.com kramar_nec@rediffmail.com ann_aji@rediffmail.com
Number of paper pages: 12
Abstract: From the single core to the dual core and then to multicore homogeneous processor, the next step could be the heterogeneous processor where different researches are going on. But whatever the processor, it is necessary to use the processor more efficiently and obtain maximum utility while used in the real time system. Even thou there are many schedulers available, almost every scheduler are not giving the maximum performance when used in real time system when there is an overload. To overcome this, an innovative approach has been used in this paper which gives the maximum utility when compared to the other related schedulers available. The program is split and grouped together in the initial stage, and a section code is tested for the entire cluster of code and using the feedback loop the miss ratio is identified. The major work of the paper is selecting the desired algorithm and fixing to the desired core in the heterogeneous multicore processor. So if a deadline !
is not met by any one of the core, then the scheduler submits it to the next core of high or low end speed using the feedback control framework This gives a wider spectrum when double check is done for each code before it is used in the real time system avoiding the miss ratio and obtaining the maximum utility. The paper uses operating system scheduler algorithm over the control system methodology for its design and scheduling.
Keywords: Section code, loop cloud, MAPS
EXTENSION of the file: .pdf
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How Did you learn about congress: Jeysingh, CSI Institute of Technology, Grace Garden, Thovalai, Knayakumari District, TamilNadu, India.
IP ADDRESS: 110.172.176.2
