The following information was submitted:
Transactions: WSEAS TRANSACTIONS ON SIGNAL PROCESSING
Transactions ID Number: 29-761
Full Name: Alejandro Castillo Atoche
Position: Ph.D. Candidate
Age: ON
Sex: Male
Address: Av. Cientifìca 1145 , colonia el Bajío, Zapopan , 45015, Jalisco, México.
Country: MEXICO
Tel: 52(33) 3777-3600
Tel prefix:
Fax: 52(33) 3777-3609
E-mail address: acastillo@gdl.cinvestav.mx
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Title of the Paper: Reconfigurable Architecture of Systolic Array Processors for Real Time Remote Sensing Image Enhancement/Reconstruction
Authors as they appear in the Paper: A. Castillo Atoche, D. Torres Roman, Y. Shkvarko
Email addresses of all the authors: acastillo@gdl.cinvestav.mx, dtorres@gdl.cinvestav.mx, shkvarko@gdl.cinvestav.mx
Number of paper pages: 11
Abstract: In this paper, we propose a reconfigurable architecture of systolic array (SA) processors for near real time implementation of high-resolution reconstruction of remote sensing (RS) imagery. The proposed design is based on a Field Programmable Gate Array and performs the image enhancement/reconstruction tasks in an efficient reconfigurable processing architecture mode that involves the systolic array processors aimed to meet the (near) real time imaging systems requirements in spite of conventional computations. In particular, the reconfigurable architecture of SA processors is employed with the objective to decrease the computational load of the large-scale RS image enhancement/reconstruction tasks required to implement the RS enhancement/reconstruction algorithms based on the descriptive regularization techniques with the corresponding iterative fixed-point Projection Onto Convex Sets unified via the proposed Hardware/Software Co-Design paradigm.
Keywords: Remote sensing, Reconfigurable architecture, FPGA, Systolic array processors, Hardware/Software co-design.
EXTENSION of the file: .pdf
Special (Invited) Session: Reconfigurable Architecture of Systolic Array Processors for Remote Sensing Applications
Organizer of the Session: 617-419
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