The following information was submitted:
Transactions: WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS
Transactions ID Number: 89-491
Full Name: Neha Arora
Position: Assistant Professor
Age: ON
Sex: Female
Address: FET-MITS
Country: INDIA
Tel: +91-9828960174
Tel prefix:
Fax:
E-mail address: neha.241986@gmail.com
Other E-mails: tripsha@gmail.com
Title of the Paper: Adiabatic and Standard CMOS interfaces at 90nm Technology
Authors as they appear in the Paper: Neha Arora, B.P.Singh, Tripti Sharma, K.G.Sharma
Email addresses of all the authors: neha.241986@gmail.com, bpsingh@ieee.org, tripsha@gmail.com, sharma.kg@gmail.com
Number of paper pages: 11
Abstract: Adiabatic circuits and standard CMOS logic are widely employed in Low power VLSI chips to achieve high system performance. The power saving of adiabatic circuit can reach more than 90% compared to conventional static CMOS logic.The clocking schemes and signal waveforms of adiabatic are different from those of standard CMOS circuits. This paper investigates the design approaches of low power interface circuits in terms of energy dissipation. Several low power interface circuits that convert signals between adiabatic logic and standard CMOS circuits are presented. With BSIM3v3 90nm CMOS technology, the energy consumption of proposed interface circuits has relatively large power saving over the wide range of frequencies. This paper also investigates the different power delay product over the wide range of supply voltages. Power dissipation has been calculated for different values of temperature.The proposed circuits are showing the best results on various ranges of t!
emperature. Simulation has been done on tanner EDA tool at BSIM3v3 90nm technology.
Keywords: Standard CMOS logic, Adiabatic circuit, Interfaces, Low power, Power delay Product, Energy
EXTENSION of the file: .pdf
Special (Invited) Session: Energy Efficient Interface Circuits Between Adiabatic and Standard CMOS Logic at 90nm Technology
Organizer of the Session: 643-412
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IP ADDRESS: 115.113.187.2
