The following information was submitted:
Transactions: WSEAS TRANSACTIONS ON COMPUTERS
Transactions ID Number: 42-418
Full Name: Jorge Silva
Position: Associate Professor
Age: ON
Sex: Male
Address: Av. Trabalhador Saocarlense, 400
Country: BRAZIL
Tel: +551633738168
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Fax:
E-mail address: jsilva@icmc.usp.br
Other E-mails: joelmir@icmc.usp.br
Title of the Paper: A Dynamic Data ow Architecture using partial recon gurable hardware as an option for multiple cores
Authors as they appear in the Paper: Joemlir Lopes, Jorge Silva
Email addresses of all the authors: joelmir@icmc.usp.br, jsilva@icmc.usp.br
Number of paper pages: 20
Abstract: Different from traditional processors, Moore´s Law was one of the reasons to duplicate cores, and at least until today it is the solution for safe consumption and operation of systems using millions of transistors. In terms of software, parallelism will be a tendency over the coming years. One of the challenges is to create tools for programmers who use HLL (High Level Language) producing hardware directly. These tools should use the utmost experience of the programmers and the flexibility of FPGA (Field Programmable Gate Array). The main aspect of the existing tools which directly convert HLL into hardware is dependence graphics. On the other hand, dynamic dataflow architecture has implicit parallelism. ChipCflow is a tool to convert C directly into hardware that uses FPGA as a partial reconfiguration based on dynamic dataflow architecture. In this paper, the relation between traditional dataflow architecture and contemporary architecture, as well as the main char!
acteristics of the ChipCflow project will be presented.
Keywords: Dynamic Dataflow Architecture, C compiler, Binary representation, VHDL code, Run time reconfiguration.
EXTENSION of the file: .pdf
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