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Transactions: WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS
Transactions ID Number: 31-454
Full Name: Jiann-Chyi Rau
Position: Assistant Professor
Age: ON
Sex: Male
Address: 151, Ying-Chuan Rd. Tamsui, Taipei Country, Taiwan 25137
Country: TAIWAN
Tel: +886-2-2621565 ext. 2729
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Fax: +886-2-26209814
E-mail address: jcrau@ee.tku.edu.tw
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Title of the Paper: The Efficient TAM Design for Core-Based SOCs Testing
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Number of paper pages: 10
Abstract: This paper presents a framework and an efficient method to determine SOC test schedules. We increase the test TAM widths by the framework. Our method deals with the traditional scan chains and reconfigurable multiple scan chains. Experimental results for ITC¡¦02 SOC TEST Benchmarks show that we obtain better test application time when compared to previously published algorithms. Test access mechanism (TAM) and test schedule for System-On-chip (SOC) are challenging problems. Test schedule must be effective to minimize testing time, under the constraint of test resources. This paper presents a core section method based on generalized 2-D rectangle packing. A core cuts into many pieces and utilizes the design of reconfigurable core wrappers, and is dynamic to change the width of the TAM executing the core test. Therefore, a core can utilize different TAM width to complete test.
Keywords: SOC Testing, TAM, Testing Scheduling
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