The following information was submitted:
Transactions: WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS
Transactions ID Number: 32-277
Full Name: Chua-Chin Wang
Position: Professor
Age: ON
Sex: Male
Address: 70, Lian-Hai Rd.
Country: TAIWAN
Tel: 7-5252000 ext.4144
Tel prefix: +886
Fax: 7-5254199
E-mail address: ccwang@ee.nsysu.edu.tw
Other E-mails: ccwang@mail.nsysu.edu.tw
Title of the Paper: LVDS Transceiver Using Common Mode DC Biasing
Authors as they appear in the Paper: Chua-Chin Wang,Chia-Hao Hsu,Jian-Ming Huang,Ron-Chi Kuo
Email addresses of all the authors: ccwang@ee.nsysu.edu.tw,chhsu@vlsi.ee.nsysu.edu.tw,sisyphe@vlsi.ee.nsysu.edu.tw,krchi@vlsi.ee.nsysu.edu.tw
Number of paper pages: 10
Abstract: LVDS has become a popular choice for high-speed serial links in large-sized display units. This work presents the design and implementation of I/O interface circuits for Gbps operation which is fully complied with the IEEE STD. 1596.3 (LVDS). A step-down voltage regulator is employed to reject the noise coupled in the system power supply. A DC biasing circuitry is utilized in the transmitter to stabilize the common mode voltage in a pre-defined range. Additionally, a regenerative circuit provides a positive feedback loop gain between the cascaded preamplifiers and the output buffer in the receiver. A typical 0.25 um 1P5M CMOS technology is used to realize the proposed LVDS transceiver. The data rate has been justified on silicon to be 1.0 Gbps.
Keywords: LVDS signaling, Regulator, Positive feedback, Common mode DC biasing, High-speed D-latch
EXTENSION of the file: .pdf
Special (Invited) Session:
Organizer of the Session:
How Did you learn about congress: NSYSU Library, 70, Lian-Hai Rd. Kaohsiung, Taiwan 80424, cirlib@mail.nsysu.edu.tw
IP ADDRESS: 218.173.18.213
