The following information was submitted:
Transactions: WSEAS TRANSACTIONS ON COMPUTERS
Transactions ID Number: 31-562
Full Name: Zuo Wang
Position: Ph.D. Candidate
Age: ON
Sex: Male
Address: 5 South Zhongguancun Street,Haidian District,Beijing
Country: CHINA
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E-mail address: qiushui@bit.edu.cn
Other E-mails: 329695344@qq.com
Title of the Paper: triplet-based topology for on-chip networks
Authors as they appear in the Paper: Wang Zuo, Zuo Qi, Li Jiaxin
Email addresses of all the authors: qiushui@bit.edu.cn, Zqll27@bit.edu.cn, starforce@bit.edu.cn
Number of paper pages: 10
Abstract: Most CMPs use on-chip network to connect cores and tend to integrate more simple cores on a single die. As the number of cores increases, the on-chip network will play an important role in the performance of future CMPs. Due to the tradeoff between the performance and area constraint in on-chip network designs, we propose the use of triplet-based topology in on-chip interconnection networks and demonstrate how a 9-node triplet-based topology can be mapped to on-chip network. By using group-caching protocol to exploit traffic locality, triplet-based topology offers lower latency and energy consumption than 2D-MESH. We run multithreaded commercial benchmarks on multi-core simulator GEMS to generate practical traffics and simulate these traffics on network simulator Garnet. Our experiment results show that triplet-based network can increase the work-related throughput by 3%~11% and reduce average network latency by 24%~32% compared with 2D-MESH, with the router energy!
consumption reduced by 13%~16% and the link energy consumption reduced by 14%~16%.
Keywords: On-chip network, Cache protocol, Network latency, Energy consumption, Performance, Mapping
EXTENSION of the file: .pdf
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