The following information was submitted:
Transactions: WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS
Transactions ID Number: 31-688
Full Name: Kaushik Bhattacharyya
Position: Researcher
Age: ON
Sex: Male
Address: E&ECE Department, IIT-Kharagpur
Country: INDIA
Tel: 0919434252606
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E-mail address: kaushik@ece.iitkgp.ernet.in
Other E-mails: bhattacharyya_kaushik@yahoo.com
Title of the Paper: Architectural Design of a Radix-4 CORDIC Based
Authors as they appear in the Paper: Kaushik Bhattacharyya, Swapna Banerjee
Email addresses of all the authors: kaushik@ece.iitkgp.ernet.in; swapna@ece.iitkgp.ernet.in
Number of paper pages: 25
Abstract: This paper addresses the problem of conventional FFT/IFFT problem in high speed applications. When the number of data points are the power of four at that time it is wise able to use radix-4 algorithm instead of using the conventional radix-2 algorithm. Here a 16 point radix-4 IFFT algorithm is taken into consideration. It offers fewer multiplications than the processors using radix-2.Number of stages are also minimum in comparison to the other. A novel and simple architecture of this IFFT algorithm is presented. It includes pipelining and parallelism in together. With the concurrent use of pipelining and parallelism the advantages of minimization of latency time and the increment of the throughput rate can be achieved. This architecture incorporates Radix-4 CORDIC which provides almost multiplier less architecture. The whole radix-4 CORDIC based radix-4 IFFT architecture is implemented on a FPGA device at operating frequency of 50 MHz with the accuracy up to 32 !
bit precision. Only 43% of the total area is consumed by the implemented architecture
Keywords: 16pt Radix-4 IFFT; Radix-4 CORDIC; VLSI Architecture; Pipelining; Parrallelism; Throughput; Latency; FPGA Implementation
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