Thursday, 13 November 2008

Wseas Transactions

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Transactions: WSEAS TRANSACTIONS ON SYSTEMS
Transactions ID Number: 31-710
Full Name: Yang Han
Position: Ph.D. Candidate
Age: ON
Sex: Male
Address: Department of electrical engineering,Shanghai JiaoTong University,1954 HuaShan Road,Shanghai,P.R.China
Country: CHINA
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E-mail address: hanhansjtu@yahoo.com
Other E-mails: xingxuepiaoling@sjtu.edu.cn
Title of the Paper: A Novel Control Strategy for Dynamic Voltage Restorer using Decoupled Multiple Reference Frame PLL (DMRF-PLL)
Authors as they appear in the Paper: Lin Xu, Yang Han, M.M.Khan, Lidan Zhou, Gang Yao, Chen Chen, Junmin Pan
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Number of paper pages: 17
Abstract: This paper presents a new control scheme for dynamic voltage restorer (DVR), which consists of a set of series and shunt converters connected back-to-back (BTB), three series transformers, and a dc capacitor installed on the common dc-link. The DVR is characterized by installing the shunt converter on the source side and the series converter on the load side. A decoupled multiple reference frame phase-locked-loop (DMRF-PLL) is proposed, which decouples signals of different frequencies and eliminates interactions between the fundamental-frequency positive-sequence components and harmonic and/or negative-sequence components in the grid voltages. The proposed DMRF-PLL scheme achieves a fast, precise, and robust positive-sequence voltage detection even under unbalanced and/or distorted grid voltages conditions. A detailed description and derivation of the detection method is presented. Besides, a separate proportional-integral (PI) controller is adopted to regulate the!
dc-link capacitor voltage. The load voltage waveform is restored to be sinusoidal with fundamental frequency by dynamically injecting compensating voltages to the series brunch of converters. The validity and effectiveness of the presented scheme has been confirmed by extensive simulation results obtained from a 380V/50kVA system using Matlab/Simulink.
Keywords: Dynamic voltage restorer, decoupled multiple reference frame phase locked loop (DMRF-PLL), voltage sag detection, dc capacitor control, series converters, shunt converters, harmonic and unbalanced voltage compensation.
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