The following information was submitted:
Transactions: WSEAS TRANSACTIONS ON COMPUTERS
Transactions ID Number: 27-647
Full Name: Yung-Yuan Chen
Position: Professor
Age: ON
Sex: Male
Address: No. 707, Sec. 2, Wu-Fu Rd., Hsin-Chu
Country: TAIWAN
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E-mail address: chenyy@chu.edu.tw
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Title of the Paper: Datapath Error Detection with No Detection Latency for High-Performance Microprocessors
Authors as they appear in the Paper: Yung-yuan Chen, Kuen-long Leu, Kun-chun Chang
Email addresses of all the authors: chenyy@chu.edu.tw, 945401025@cc.ncu.edu.tw, m09402023@cc.chu.edu.tw
Number of paper pages: 15
Abstract: Error detection plays an important role in fault-tolerant computer systems. Two primary parameters concerned for error detection are the coverage and latency. In this paper, a new, hybrid error-detection approach offering a very high coverage with zero detection latency is proposed to protect the data paths of high-performance microprocessors. The feature of zero detection latency is essential to real-time error recovery. The hybrid error-detection approach is to combine the duplication with comparison, triple modular redundancy (TMR) and self-checking mechanisms to construct a formal framework, which allows the error-detection schemes of varying hardware complexity, performance and error-detection coverage to be incorporated. An experimental 32-bit VLIW core was employed to demonstrate the concept of hybrid detection approach. The hardware implementations in VHDL and simulated fault injection experiments were conducted to measure the interesting design metrics, su!
ch as hardware overhead, performance degradation and error-detection coverage.
Keywords: Concurrent error detection, Error-detection coverage, Error-detection latency, Fault injection, Hybrid detection approach.
EXTENSION of the file: .pdf
Special (Invited) Session: datapath error detection using hybrid detection approach for high-performance microprocessors
Organizer of the Session: 591-242
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