The following information was submitted:
Transactions: WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS
Transactions ID Number: 28-386
Full Name: Leila Koushaeian
Position: Ph.D. Candidate
Age: ON
Sex: Female
Address: School of ELectrical Engineering , Ballart Rd. Footscray Park Campus
Country: AUSTRALIA
Tel: 9919 4767
Tel prefix: 0061 3
Fax:
E-mail address: leila.koushaeian@live.vu.edu.au
Other E-mails:
Title of the Paper: Low Power Shift Register using MTCMOS Edge-Trigger D Flip Flop Transmission Gate in Sub-threshold Region
Authors as they appear in the Paper: Sameh Andrawes, Leila Koushaeian, Ronny Veljanovski
Email addresses of all the authors: Leila.koushaeian@live.vu.edu.au,sameh.andrawes@live.vu.edu.au,Ronny.Veljanovski@vu.edu.au
Number of paper pages: 10
Abstract: — low power design is much in demand nowadays due to scaling down the technology where minimizing the voltage level is the most effective way to minimize the power consumption. This paper presents the design and implementation of a low power Complementary Metal Oxide Semiconductor (CMOS) ten-bit shift register by using negative latch D Flip-Flop (DFF) in the sub-threshold region with high speed in the active mode and low power consumption during the sleep mode using Multi-threshold Complementary Metal Oxide Semiconductor (MTCMOS) technique. The circuit was implemented in 90 nm from STM CMOS technology, with oxide thickness of 16A0, 250 mV power supply, 5 MHz clock frequency with 10 % activity, average power consumption is 6.43 nW and power delay product (PDP) is 24.43 aJ. The shift register has been designed and simulated by using Cadence tools.
Keywords: leakage, low power, MTCMOS, Sub-threshold, Shift register.
EXTENSION of the file: .doc
Special (Invited) Session: Low Power Shift Register using MTCMOS Edge-Trigger D Flip Flop Transmission Gate in Sub-threshold Region
Organizer of the Session: 587-377R
How Did you learn about congress:
IP ADDRESS: 202.7.193.29
