The following information was submitted:
Transactions: WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS
Transactions ID Number: 88-360
Full Name: Kiran Bailey
Position: Lecturer
Age: ON
Sex: Female
Address: No.44, 31st main, ITI layout, JP Nagar I phase, Bangalore-560078
Country: INDIA
Tel: 9481787724
Tel prefix: 91
Fax:
E-mail address: kiranbailey@gmail.com
Other E-mails: mkchechu@gmail.com
Title of the Paper: Modeling and Performance evaluation of UTB SGOI Devices scalable to 22 nm Technology node
Authors as they appear in the Paper: Kiran Bailey , K.S. Gurumurthy
Email addresses of all the authors: kiranbailey@gmail.com, drksgurumurthy@gmail.com
Number of paper pages: 10
Abstract: There is a limit for classical CMOS devices' scaling. So to keep the Moore's law in force, attempts are being made to explore the possibility of designing newer devices. These attempts are in the direction of optimizing the design for high performance and low power applications. Silicon- Germanium on Insulator (SGOI) MOSFET is one such device which has got a bright future. An Attempt has been made in this paper to design 2D SGOI MOSFET using a commercial Technology CAD (TCAD) tool. Development of SGOI based Ultra thin Body (UTB) MOSFETs are proposed in this work. Device Simulations were performed for various Gate lengths, Body thicknesses, Anti punch doping and Si cap layer doping. It was found that, for a given body thickness and gate length, increasing the Silicon cap doping and anti-punch doping, the transconductance remains unchanged while Ioff, Drain Induced Barrier lowering (DIBL), Subthreshold slope and threshold voltages show improvement. Also, the device!
s with gate lengths 45nm, 32nm and 22nm demonstrate very good performance such as low leakage currents and good on current that are comparable to ITRS and hence can be implemented for sub-30 nm gate length devices. Device doping profiles have been optimized for the 22nm gate length CMOS devices to obtain minimum leakage and minimum static power dissipation. The performance of these devices has been evaluated by incorporating them in a Ring Oscillator and analyzing the circuit for static power dissipation and delay. The Ring oscillator consists of 3 inverter stages and with each inverter stage having a lumped capacitance of 6 MOSFETs.
Keywords: UTB MOSFETs, SGOI, Leakage currents, DIBL, Subthreshold Slope, Ring Oscillator (RO), TCAD
EXTENSION of the file: .pdf
Special (Invited) Session: Analysis and Modeling of High Performance and Low Power UTB SGOI Devices Scalable to sub 30 nm
Organizer of the Session: 102-257
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