The following information was submitted:
Transactions: WSEAS TRANSACTIONS ON SYSTEMS
Transactions ID Number: 52-342
Full Name: Geetanjali Sharma
Position: Assistant Professor
Age: ON
Sex: Female
Address: Mody Institute of Technology & Science,Laxmangarh, Sikar,Rajasthan,India
Country: INDIA
Tel: 09785140808
Tel prefix:
Fax:
E-mail address: rhytham.1987@gmail.com
Other E-mails: gsharma.et@mitsuniversity.ac.in
Title of the Paper: Power/Area Minimization using Hybrid PTL/CMOS Logic at 90 nm Technology
Authors as they appear in the Paper: Geetanjali Sharma,Uma Nirmal,Yogesh Misra
Email addresses of all the authors: rhytham.1987@gmail.com,nirmaluma1012@gmail.com
Number of paper pages: 10
Abstract: We present a hybrid PTL/CMOS logic synthesis method based on BDD (Binary decision diagram) and compared the results with their conventional static CMOS in terms of various design constraints as area, power and power delay product in an experimental BSIM3V3 90 nm technology. This approach uses multilevel PTL logic cells that are automatically constructed from only a few basic cells and determine the best mixture of PTL and CMOS cells using BDD. Experimental results shows that proposed hybrid PTL/ CMOS full subtractor gives best results over Pass transistor and CMOS logic based full subtractor.
Keywords: decision diagram (BDD), Digital CMOS, Pass transistor logic (PTL),
EXTENSION of the file: .doc
Special (Invited) Session:
Organizer of the Session:
How Did you learn about congress:
IP ADDRESS: 59.98.160.108
