The following information was submitted:
Transactions: WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS
Transactions ID Number: 52-318
Full Name: Padmanabhan Balasubramanian
Position: Doctor (Researcher)
Age: ON
Sex: Male
Address: School of Computer Science, The University of Manchester, Oxford Road, Manchester M13 9PL
Country: UNITED KINGDOM
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E-mail address: padmanab@cs.man.ac.uk
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Title of the Paper: A Standard Cell Based Synchronous Dual-Bit Adder with Embedded Carry Look-ahead
Authors as they appear in the Paper: Padmanabhan Balasubramanian, Krishnamachar Prasad, Nikos E. Mastorakis
Email addresses of all the authors: padmanab@cs.man.ac.uk, krishnamachar.prasad@aut.ac.nz, mastor@hna.gr
Number of paper pages: 10
Abstract: A novel synchronous dual-bit adder design, realized using the elements of commercial standard cell libraries, is presented in this article. The adder embeds two-bit carry look-ahead generator functionality and is realized using simple and compound gates of the standard cell library. The performance of the proposed dual-bit adder design is evaluated and compared vis-à-vis the conventional full adder (implemented using two half adder blocks) and the library's full adder element, when performing 32-bit addition on the basis of the fundamental carry propagate adder topology. Based on experimentations targeting the best case process corner of the high-speed 130nm UMC CMOS cell library and the highest speed corner of the inherently power optimized 65nm STMicroelectronics CMOS standard cell library, it has been found that the proposed adder module is effective in achieving significant performance gains even in comparison with the commercial library based adder whilst faci!
litating reduced energy-delay product.
Keywords: Adder, High-speed, Low power, PDP, EDP, Standard cells, Semi-custom design style.
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