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Transactions: WSEAS TRANSACTIONS ON SYSTEMS
Transactions ID Number: 53-103
Full Name: Changhong Yu
Position: Ph.D. Candidate
Age: ON
Sex: Male
Address: Department of Information & Electronic Engineering,Zhejiang Gongshang University Hangzhou City Zhejiang Provinice China
Country: CHINA
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E-mail address: yuch_2007@163.com
Other E-mails: hangzhouyu@gmail.com
Title of the Paper: Design of On-line Clock Jitter Fault Detection Circuit for Time-Error-Tolerant System
Authors as they appear in the Paper: Changhong Yu
Email addresses of all the authors: yuch_2007@163.com
Number of paper pages: 10
Abstract: One of the major obstacles encountered in design of a system on chip (SoC) arises from the high fault rate of clock distribution network in embedded intellectual property (IP) cores. With technology scaling, the geometries of devices approach its physical limits of operation, SoCs will be susceptible to various noise sources such as crosstalk, coupling noise, process variations, etc. Designing such a system under uncertainty becomes a challenge, as it is difficult to predict the time behavior of the system. Conservative design methodologies that consider all possible faults due to the noise sources, targeting safe system operation under all conditions will cause poor system performance. By contraries, aggressive design approach that can provide resilience against such timing faults without much additional hardware, is toughly required for maximizing system performance. In this paper we present an aggressive method to on-line detect the jitter faults on the clock s!
ignal that are due to defects caused by noise for high speed SoCs. Only fourteen MOS transistors and two minor capacitors are used for the circuit. The technique of time-to-voltage conversion is employed for transforming the time jitter error to variable voltage, which is more convenient in contrast with the conservative clock fault tolerance structure methodology. The circuit proposed can detect the jitter error of the digital clock signal faults with different applications. We have formally evaluated the meta-stability of our technique, which shows that our technique reliably meets the timing requirements. The simulation-based results show that the proposed circuit can be integrated into the nano-electronic SoCs applications to achieve the on-line clock jitter fault detection, and its maximal frequency can reach 800MHz. Furthermore, fault injection experiments show that our technique can tolerate all single faults on clock sources that lead to permanent stuck-at fault and!
masks almost 49 percents of intermittent faults
Keywords: clock fault, on-line detection, time-to-voltage conversion
EXTENSION of the file: .doc
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