The following information was submitted:
Transactions: WSEAS TRANSACTIONS ON SIGNAL PROCESSING
Transactions ID Number: 53-137
Full Name: Krishnaswamy natarajan Vijeyakumar
Position: Lecturer
Age: ON
Sex: Male
Address: Department of Electronics and Communication Engineering, Anna University of Technology, Coimbatore, Coimbatore - 641 047.
Country: INDIA
Tel: +919942377050
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E-mail address: vijey.tn@gmail.com
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Title of the Paper: design of power efficient full adder using keeper circuit
Authors as they appear in the Paper: Krishnaswamy natarajan.Vijeyakumar, Vembu Sumathy, Mahendran Nithya, Chinnaraj Venkatnarayanan, Velusamy Thiruchitrabala
Email addresses of all the authors: vijey.tn@gmail.com , sumi2001_gct@yahoo.co.in, nitmahendran@yahoo.co.in , vimhalc@gmail.com , thiruchitrabala@gmail.com
Number of paper pages: 10
Abstract: CMOS technology is approaching the nano-electronics range nowadays, but experiences some practical limits. High leakage current in deep submicron technologies are becoming a major contributor to total power dissipation of CMOS circuits as the threshold voltage, channel length and gate oxide thickness are scaled. Consequently identification and modeling of different leakage components is very important for estimation and reduction of leakage power in scaled CMOS circuits, especially for low power applications. The ongoing technology trend will become difficult to maintain unless dedicated library cells, new logic styles and circuit methods are emerging to rectify the shortcomings of future nano-scale circuits. The logic styles used in the design of CMOS full adder circuit have many limitations in terms of power and number of transistors. Hybrid full adder is designed in which the sum and carry blocks are connected to supply through a keeper circuit. Keeper circui!
t keeps the main circuit active only during the active part of input signal and also acts as a level restorer. This reduces the leakage power dissipation thereby decreasing the total power dissipation. The proposed adder blocks are designed and simulated using TSPICE. Fabrication technology used is 180nm. Performance of the proposed adder design is analyzed in terms of power, delay and power delay product (PDP). Analysis shows that the proposed power efficient adder is superior in performance to BBL-PT (Branch-Based Logic Pass- transistor) adder.
Keywords: Branch-Based Logic, Pass- transistor logic, logic depth, Hybrid full adder , Pseudo nMOS, Keeper circuit, Power efficient adder.
EXTENSION of the file: .pdf
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