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Transactions: WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS
Transactions ID Number: 89-195
Full Name: Wen-Tzeng Huang
Position: Professor
Age: ON
Sex: Male
Address: No.1, Xinxing Rd., Xinfeng Hsinchu 30401
Country: TAIWAN
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E-mail address: wthuang@must.edu.tw
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Title of the Paper: A Novel Design for Evaluating Simultaneous Switching Noise within an Enhanced IBIS Model
Authors as they appear in the Paper: Wen-Tzeng Huang, Sun-Yen Tan, Yuan-Jen Chang, Chiu-Ching Tuan
Email addresses of all the authors: wthuang@must.edu.tw, sytan@ntut.edu.tw, ronchang@ctust.edu.tw, cctuan@ntut.edu.tw
Number of paper pages: 18
Abstract: Simultaneous switching noise (SSN) is a major cause of power integrity (PI) degradation that causes circuits to become unstable and experience errors. As modern ICs operate at higher speeds with higher density and lower voltages, SSN has become a serious issue that must be addressed to ensure system stability during the short rise- and fall-times of the logic transient states. Most traditional designs have generally used decoupling capacitors to reduce SSN. As these capacitors become equivalent series inductances when the system operates at high frequencies, such a technique works against reducing SSN. Therefore, we propose a methodology called the enhanced IBIS model that effectively alleviates the problem of SSN using an evaluation based on the enhanced I/O buffer information specification (IBIS) model with decoupling capacitors and a high-frequency low-impendence circuit. In this study, we showed that SSN from 452 mV, 290 mV, 163 mV, and 301 mV, of IBIS, traditi!
onal decoupling capacitors, IBIS with a high-frequency low-impendence circuit, and HP Simulation Program with Integrated Circuit Emphasis (HSPICE) methodologies, respectively, was effectively reduced by 121 mV of our enhanced IBIS mode as measured by the peak-to-peak value. That is, our new method reduces noise by more than 73.2%, 58.3%, 25.7%, and 59.8% compared to other four methodologies, respectively.
Keywords: Simultaneous Switching Noise (SSN), Power Integrity (PI), I/O Buffer Information Specification (IBIS), HSPICE, High-frequency low-impedance (HFLI) circuit.
EXTENSION of the file: .pdf
Special (Invited) Session: A Noise-aware Design and an Enhanced IBIS Model for Evaluating Simultaneous Switching Noise
Organizer of the Session: 697-630
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